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GLOBALFOUNDRIES Qualifies Synopsys Fusion Design Platform on 12LP FinFET Platform

Auto News - Published on Thu, 17 Oct 2019

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Synopsys announced that GLOBALFOUNDRIES has qualified Synopsys’ Fusion Design Platform for its 12-nanometer (nm) Leading-Performance FinFET platform. Optimized for the high-performance and low-power requirements of artificial intelligence (AI), cloud computing, and mobile system-on-chips (SoCs), the production-ready flow is based on the silicon-proven RTL-to-GDSII 12LP foundry reference flow and incorporates Synopsys Advanced Fusion technologies for best quality-of-results and time-to-results in FinFET designs.

The Synopsys Fusion Design Platform optimized for GF’s 12LP FinFET platform utilized the latest enhancements in the digital implementation and signoff flow to maximize GF’s 12LP performance and power benefits. Advanced RC modeling and pin access optimization in Design Compiler Graphical and Design Compiler NXT synthesis solutions enable tighter correlation with IC Compiler II place-and-route, leading to faster design convergence. Logic restructuring, a key feature of Advanced Fusion Technology, enables fast area, timing, power, or congestion-based re-synthesis. ECO Fusion reduces the need for excessive engineering change order iterations by allowing rapid design changes during the physical implementation, resulting in faster timing convergence.

The key tools and technologies of the Synopsys Fusion Design Platform certified for GF’s 12LP FinFET platform include:

IC Compiler II place-and-route with Advanced Fusion Technology: Fully automated flow with comprehensive GF 12LP rules support. Deployment of advanced legalizer, pin density-aware placement, total power optimization, logic restructuring, and ECO closure.

Design Compiler Graphical and Design Compiler NXT RTL synthesis: Advanced power, performance, and area (PPA) optimizations, congestion reduction, pin access-aware optimization, tight correlation, and physical guidance for IC Compiler II.

IC Validator physical signoff: Physical signoff including DRC, LVS, and Fill. Innovative Explorer DRC and Live DRC technologies for enhanced productivity.

PrimeTime timing signoff: Advanced variation modeling for low voltages, and enhanced ECO technologies with support for new physical design rules.

StarRC extraction signoff: Advanced modeling to handle the complexity of FinFET devices, as well as a common technology file for parasitic extraction consistency from synthesis to place-and-route to signoff.

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Posted By : Mohan Sharma on Thu, 17 Oct 2019
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